The M4WIS adds four-wire slave capability to the M8051W and M8051EW designs that is compatible with the I2C Fast protocol. Clock stretching can be achieved under register control in order to implement flow control. Use of standard synchronous design methodology makes this core simple to integrate into both ASIC SoC and FPGA designs.

The M4WIS is designed to bind tightly to an M8051W or M8051EW SFR bus. Data, control and status information are exchanged with the host microcontroller using memory-mapped 8-bit words. A single interrupt signal is used to indicate that a matching address has been received, that data buffers require service or that an exception has been detected. Use of standard synchronous design methodology makes this core simple to integrate into both ASIC SoC and FPGA designs.

Download The M4WIS Datasheet Here