The M8051EW is a high performance core that executes each machine cycle in two clock cycles, giving a clock-for-clock performance that is six times faster than the M8051 and M8052 cores. They remain, however, binary and memory cycle compatible with Intel MCS-51 devices.
The M8051EW incorporate various extended features, such as extra data pointers, support of extra interrupts and interrupt priority levels, optional multiple clock domains for optimising power consumption and support for synchronous memory cells.
The M8051EW also includes a rich hardware debugger and a JTAG debug port that supports external debugger environments. Hardware breakpoints, instruction traceback and full read/write access to all registers and memories are supported. We recommend the FS2 System Navigator debug system, for which the M8051EW on-chip instrumentation was originally designed.
