LONDON, UNITED KINGDOM.
Syntill8 Ltd. has now released version 5.0 of the M8051W 8-bit microcontroller IP core, which includes performance enhancements, tool flow updates and productivity enhancements.
Key Enhancements Include
- Single Machine-cycle MOVX and MOVC instructions to replace current two-cycle execution time for these heavily used instructions.
- Improvement of maximum clock speed: The current critical path used by conditional branch instructions is now approximately halved.
- Peripheral clock pre-scalers, for matching performance to power consumption.
- Array of up to eight pulse width modulators, with optional up/down ramping.
- Two-Wire Master Interface, compatible with I2C 'F' protocol.
- Four-Wire SPI-compatible Master Interface.
- Watchdog timer with warning interrupt and reset.
- Programmable stack overflow detection and reset.
Other Updates include
- External buses now held in inactive state whilst reset is applied to core.
- Added TCL Synthesis Scripts and example Scan Insertion scripts.
- Added FPGA synthesis scripts to support the Altera Quartus flow, using SDC format for timing constraints.
- Unified the Verilog and VHDL synthesis script set.
- Documentation enhancements to the external memory interfaces and wait state system descriptions.
Both the M8051W microcontroller core and support services are available from Syntill8. Standard deliverables include: synthesizable RTL source code and testbenches in both Verilog and VHDL, simulation scripts, example netlist, in-depth documentation, and example synthesis and DFT scripts for Mentor and Synopsys flows. For more information view the M8051W data sheet and/or contact us for more detailed information.