London, United Kingdom.
August 6, 2013
Syntill8 ltd. today announced new product development of the UDPMAC, a 1-Gigabit UDP/Ethernet Media Access Controller (MAC) IP core. The UDPMAC provides an Ethernet MAC interface and UDP datagram interface to the M8051W and M8051EW microcontroller IP cores using integral DMA and configurable packet FIFOs. Use of standard synchronous design methodology makes this core simple to integrate into both ASIC SoC and FPGA implementations.
The UDPMAC implements a UDP transport layer, and IP layer functions, compatible with the RFC768 and RFC791 protocols. It also includes Ethernet MAC functionality that is compatible with the RFC894 protocol. The UDPMAC interfaces to an external PHY using the four-wire RGMII gigabit interface. The PHY can be controlled using the UDPMAC via a four-wire MDIO interface. The UDPMAC is designed to bind closely to the M8051W and M8051EW with minimal additional glue logic, and is compatible with the standard M8051W and M8051EW three power saving states.
The core RTL is highly configurable at compile time allowing users to implement only the features required by their application.
Major Configuration Options Include
- DMA or FIFO based data path
- Configurable data FIFO depths up to 1500 bytes
- Single clock design, or independent MAC and microcontroller clock domains
- User defined SFR base address
- User defined interrupt channel
- Optional microcontroller wake-up signal on MAC address match, MAC broadcast, IP address match, or IP and port address match